A positive voltage charge-pump is a DC-DC voltage converter that operates to convert an input voltage to an output voltage having a magnitude that is higher than the input voltage. The input is, in many instances, a supply voltage for a circuit. Such charge pump circuits typically use capacitors as energy storage devices. The capacitors are switched in such a way that the desired voltage conversion occurs.
Charge pumps are useful in many different types of circuits, including low-voltage circuits, dynamic random access memory circuits, switched-capacitor circuits, EEPROM's and transceivers. In non-volatile memories, for example, charge-pumps are critical because they are used to generate the high voltages necessary to perform program and erase operations.
A charge pump circuit typically includes a basic building block referred to as a “voltage doubler” circuit. The voltage doubler circuit takes a DC input voltage (VIN) and generates an output voltage VOUT that is substantially equal to double the input voltage (i.e., 2*VIN), where “substantially equal” means at or nearly the same voltage within a tolerance range (generally less than a few percent) that is dependent voltage drop (or charge loss) across parasitic capacitances and output current load. By cascading N such voltage doubler circuit stages in series, a final output voltage that can be produced that is substantially equal to (N+1)*VIN.
An example of a prior art voltage doubler circuit 10 stage is shown in FIG. 1. This circuit 10 is commonly referred to in the art as a CMOS latch-based voltage doubler. The circuit 10 includes a latch circuit formed by two cross-coupled CMOS inverter circuits 12 and 14. The source terminals of the n-channel MOS transistors of the latch circuit are connected to an input node A (receiving the input voltage VIN) and the source terminals of the p-channel MOS transistors of the latch circuit are connected to an output node B (generating the output voltage VOUT). A capacitor C is coupled to each pair of connected drain terminals of the CMOS transistors of the latch circuit. A first capacitor coupled to inverter circuit 12 is configured to receive a clock signal CK and a second capacitor coupled to inverter circuit 14 is configured to receive a clock signal CKN (which is a logical inversion of the clock signal CK). Operation of this circuit 10 in response to the clock signals CK and CKN to double the input voltage is well known to those skilled in the art.
A voltage quadrupler circuit can be made by cascading three such voltage doubler circuit 10 stages in series as shown in FIG. 2 to produce a final output voltage VOUT that is substantially equal to 4*VIN. In comparison to other prior art cascaded circuits, the circuit of FIG. 2 advantageously does not exhibit a threshold voltage drop across the connected stages of the charge pump. Furthermore, the circuit requires just the two clock phases (CK and CKN) as applied to all stages. However, there are a number of known drawbacks including:
1) As N increases, for example when N=3 for a voltage quadrupler as in FIG. 2, the three cascaded circuit 10 stages occupy a significantly large amount of circuit area, especially due to the presence of six capacitors C whose occupied area is significant and dominates the overall area occupied by the circuit. The capacitance of each capacitor C is selected dependent on a number of different parameters including operating frequency, output current load, output capacitive load and ramp-up time of the charge pump. In general, the capacitance of each capacitor C included in the circuit is the same, and thus the overall occupied capacitor area is six times the area required for one capacitor.
2) Also, there is some charge loss across the CMOS transistor switches from one circuit stage to another circuit stage during the charge pumping operation. As an example, with an input voltage VIN=2V, the output voltages at the first, second and third voltage doubler circuit 10 stages may equal 3.96V, 5.92V and 7.89V, respectively, with the difference of 0.11V in the substantially equal output voltage representing a percentage or offset of 1.4% from the ideal 8V output voltage.
There is accordingly a need in the art for a voltage quadrupler circuit that can be used to generate an output voltage substantially equal to four times the input voltage and which occupies a reduced circuit area in comparison to prior art multi-stage cascaded charge pumps.